The development of complicated integrated circuits often requires powerful numerical simulation programs. For example, circuit simulation is an essential part in the design flow of integrated circuits, helping circuit designers to verify the functionality and performance of their designs without going through expensive fabrication processes. Examples of electronic circuit simulators include the Simulation Program with Integrated Circuit Emphasis (SPICE) developed at the University of California, Berkeley (UC Berkeley), and various enhanced versions or derivatives of SPICE, such as SPECTRE, developed by Cadence Design Systems, Inc. SPICE and its derivatives or enhanced versions will be referred to hereafter as SPICE circuit simulators, or SPICE.
An integrated circuit is a network of circuit elements such as resistors, capacitors, inductors, mutual inductors, transmission lines, diodes, bipolar junction transistors (BJT), junction field effect transistors (JFET), metal-oxide-semiconductor field effect transistors (MOSFET), metal-semiconductor field effect transistors (MESFET), thin-film transistors (TFT), etc. SPICE models a circuit in a node/element fashion, i.e., the circuit is regarded as a collection of various circuit elements connected at nodes. At the heart of SPICE is the so-called Nodal Analysis, which is accomplished by formulating nodal equations (or circuit equations) in matrix format to represent the circuit and by solving these nodal equations. The circuit elements are modeled by device models, which produce model results that are represented in the circuit equations as matrices.
A device model for modeling a circuit element, such as the SPICE model for modeling MOSFET devices, developed by UC Berkeley, typically includes model equations and a set of model parameters that mathematically represent characteristics of the circuit element under various bias conditions. For example, a circuit element with n terminals can be modeled by the following current-voltage relations:Ii=fi(V1, . . . , Vn, t) fori=1, . . . , n, where Ii represents the current entering terminal I; Vj (j=1, . . . , n) represents the voltage or terminal bias across terminal j and a reference terminal, such as the ground; and t represents the time. The Kirchhoff's Current Law implies that the current entering terminal n is given by
      I    n    =            ∑              i        =        1                    n        -        1              ⁢                  ⁢                  I        i            .      A conductance matrix of the circuit element is defined by:
      G    ⁡          (                        V          1                ,        …        ⁢                                  ,                  V          n                ,        t            )        :=            (                                                                  ∂                                  f                  1                                                            ∂                                  V                  1                                                                          ⋯                                                              ∂                                  f                  1                                                            ∂                                  V                  n                                                                                          ⋮                                ⋱                                ⋮                                                                              ∂                                  f                  n                                                            ∂                                  V                  1                                                                          ⋯                                                              ∂                                  f                  n                                                            ∂                                  V                  n                                                                        )        .  To model the circuit element under alternating current (AC) operations, the device model also considers the relationship between node charges and the terminal biases:Qi=qi(V1, . . . , Vn, t) for i=1, . . . , n. where Qi represents the node charge at terminal i. Thus, the capacitance matrix of the n-terminal circuit element is defined by
      C    ⁡          (                        V          1                ,        …        ⁢                                  ,                  V          n                ,        t            )        :=            (                                                                  ∂                                  q                  1                                                            ∂                                  V                  1                                                                          ⋯                                                              ∂                                  q                  1                                                            ∂                                  V                  n                                                                                          ⋮                                ⋱                                ⋮                                                                              ∂                                  q                  n                                                            ∂                                  V                  1                                                                          ⋯                                                              ∂                                  q                  n                                                            ∂                                  V                  n                                                                        )        .  
A complex integrated circuit may contain millions of circuit elements such as transistors, resistors, and capacitors. Integrated circuit design relies on circuit simulation to verify functionality and electrical behavior of the circuit. As the integrated circuit becomes more complex, faster simulation tools are required to simulate the whole circuit in an acceptable time frame. One of the techniques in fast simulation is by means of a table-lookup approach. The table-lookup approach uses a pre-built lookup table to store device behavior in terms of terminal currents and node charges as function of terminal biases for model evaluation. An example of a pre-built lookup table may be a three-dimensional table containing device behavior at incremental voltages between the drain and source (Vds), gate and source (Vgs), and body and source (Vbs) of a MOSFET transistor. These conventional approaches use interpolation to calculate terminal current and node charges of the devices for arbitrary biases during simulation.
Conventional table-lookup approaches may be considered as one kind of modeling of a device's quasi static (QS) behavior, where node charges and terminal currents are determined by the terminal voltage at a particular point in time only. Such conventional approaches fail to accurately model high speed submicron devices where the device's non-quasi static (NQS) behavior, such as the history of the terminal voltages, also plays a significant role in determining the behavior of the circuit. The conventional table-lookup approaches are inadequate in this regard for a number of reasons. First, if the conventional lookup table is modified to include the time dimension, it would increase the conventional three-dimensional table to a four-dimensional table, which in turn increases the amount of dynamic random access memory required by an order of magnitude in order to run circuit simulation. This approach is not only expensive but also infeasible for simulation of large designs. In addition, increasing the dimensions of the conventional lookup table also increases the evaluation time by an order of magnitude, which adversely impacts the performance of the fast SPICE simulation.
Another limitation of the conventional table-lookup approach is that it is ineffective when applied to handle a gate resistance network. For RF and high speed integrated circuit applications, especially in submicron technologies of 65 nm and below, the gate resistance is no longer negligible. The effect of the gate resistance on a device's behavior is primarily a dynamic behavior. When a gate terminal of a MOSFET transistor is charging or discharging, the gate current flows through the gate resistance, which affects the gate voltage applied to the transistor by a dynamic voltage across the gate resistance. This scenario is not addressed by the conventional table-lookup approaches because the conventional lookup tables were built statically. For this reason, the conventional lookup tables do not model the dynamic charging/discharging voltage offset caused by the gate resistance. A possible attempt to address this issue is to add a resistance at gate node outside the lookup table. But this solution creates additional issues in circuit partition and may cause convergence problems for fast SPICE simulators.
Similarly, the conventional table-lookup approach is ineffective when applies to handle substrate resistance and source-drain parasitic resistance networks. This is because the conventional lookup tables were built statically based on the external drain/source/gate/substrate voltages. This means that the conventional lookup tables only include the voltage across the parasitic resistances by static DC current. Thus, the conventional lookup tables may only account for the static voltage offset caused by those resistances, but the dynamic voltage offset, which could be much bigger than the static voltage offset during high speed transient processes, is ignored in the conventional table-lookup approach. For source/drain resistance, this may be acceptable when parasitic source/drain resistances are small. However, ignoring the dynamic voltage in the gate resistance may lead to inaccurate modeling and simulation of the devices.
Therefore, there is a need for a method and system that address the issues of the conventional table-lookup approach described above. Specifically, there is a need for a method and system for modeling integrated circuits for fast simulation.